The present invention relates to a non-volatile memory structure formed in and on a semiconductor substrate. More particularly, the invention relates to a non-volatile memory structure with a single layer of polysilicon gate and a method for fabricating the structure.
A non-volatile memory cell, a widely used semiconductor device, is capable of preserving digital information without supply of electric power. An erasable programmable ROM (EPROM), one of the non-volatile memory cells fabricated based on a semiconductor substrate, preserves digital information by trapping electrons in its floating gate when some electrodes of the EPROM are biased in desired levels. The electrons trapped in the floating gate of EPROM could be evacuated to erase the preserved information by exposing the EPROM in an environment with a high dose of ultraviolet. Since the EPROM has the feature of repeatedly recording information in a state out of supply of electric power, it is employed in many electronic devices nowadays.
Referring to FIG. 1, a typical EPROM cell is fabricated on a silicon substrate 102 doped with P-type impurities, such as B, BF2+. A silicon dioxide layer 108 formed on the surface of the P-substrate 102 encompasses a floating gate 110 and control gate 112, in which the two gates are insulated by the silicon dioxide layer 108. A source region 104 and drain region 106 doped with N-type impurities, such as P, As, are embedded at opposite two sides of the floating gate 110 in the P-type substrate 102. When recording information in the EPROM cell, the control gate 112 and drain region 106 are biased in a high voltage level, meanwhile the source region 104 and substrate 102 being electrically connected to ground, to drive electrons ejecting from the source region 104 through the silicon dioxide layer 108 into the floating gate 110. The silicon dioxide layer 108 would construct a potential barrier so as to trap the electrons in the floating gate 110. Because of the electrons trapped in the floating gate, when the control gate 112 is biased to its original threshold voltage level, the channel between the source region 104 and drain region 106 will not be normally turned on, therefore regarding this state as xe2x80x9c1xe2x80x9d. Contrarily, if the EPROM cell doesn""t be biased to eject electrons into the floating gate 110, the channel between the source region 104 and drain region 106 will be turned on, as long as the control gate 112 is biased to its threshold voltage level. Such a state would be regard as xe2x80x9c0xe2x80x9d.
To erase the preserved information, it is necessary expose the EPROM to an ultraviolet environment for providing the trapped electrons enough energy to escape from the potential barrier of the silicon dioxide layer 108. By applying the erasing and recording procedures, the EPROM cell can be repeatedly performed to preserve digital information.
Commonly, the EPROM cell includes two stacked gates, the control gate 112, and floating gate 110. To approach the two gates, it needs more complicated fabricating processes to form the two-layer structure. For forming an EPROM chip, EPROM cells are always designed in association with logic devices, such as MOSFET, CMOSFET, and so on. However, the MOSFET and CMOSFET are both one-layer structures with fewer lithographic masks than those of the EPROM cells, so as to make the fabricating processes of the EPROM cell being somewhat incompatible from that of the MOSFET and CMOSFET. For fitting the fabricating processes of the EPROM cell, the processes of the EPROM chip would become costly and complicated.
The traditional EPROM cell could provide a high integration, but in some cases the EPROM chip doesn""t need such a high integration but concerns more about the cost and simplicity of fabricating processes. Under this concern, the present invention demonstrates a single poly non-volatile memory structure and its fabricating method for improving the disadvantages existed in the prior art.
A first object of the invention is to provide a non-volatile memory structure with a single-layer poly gate design for simplifying the fabricating processes of the structure so as to fit the processes with those of logic devices, such as MOSFET and CMOSFET.
A second object of the invention is to provide a method to approach the single polysilicon non-volatile memory structure.
The present invention provides a single poly non-volatile memory structure including a P-type doped semiconductor substrate, in which an N-well is formed, divided into two active areas by isolation regions. A control gate is embedded in the first active area by implanting N-type impurities into the N-well. A first floating gate as well as a second floating gate are formed on the control gate and the second active area through subsequently stacking an oxide, polysilicon, and silicide layers on the substrate, and then etching the oxide-polysilicon-silicide composite layer. Two doped regions are formed at opposite two sides of the second floating gate in the second active area by implanting N-type impurities. A floating gate line is formed to electrically connect the first floating gate and second floating gate for making sure that they would keep in the same potential. When the control gate is biased to a voltage level, the voltage level would be coupled to the first floating gate so as to keep the second floating gate in the same potential with the first floating gate. While one of the doped regions is biased to a voltage level, electrons would eject from the other doped region and be trapped in the floating gates, thereby preserving information in this memory structure.